View LSM303DLHCTR_6501557.PDF datasheet online --- IC-ON-LINE

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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. april 2011 doc id 018771 rev 1 1/42 42 lsm303dlhc ultra compact high performance e-compass 3d accelerometer and 3d magnetometer module features 3 magnetic field channels and 3 acceleration channels from 1.3 to 8.1 gauss magnetic field full- scale 2g/4g/8g/16g se lectable full-scale 16 bit data output i 2 c serial interface analog supply voltage 2.16 v to 3.6 v power-down mode/ low-power mode 2 independent programmable interrupt generators for free-fall and motion detection embedded temperature sensor embedded fifo 6d/4d orientation detection ecopack ? rohs and ?green? compliant applications compensated compass map rotation position detection motion-activated functions free-fall detection click/double click recognition pedometer intelligent power-saving for handheld devices display orientation gaming and virtual reality input devices impact recognition and logging vibration monitoring and compensation description the lsm303dlhc is a system-in-package featuring a 3d digital linear acceleration sensor and a 3d digital magnetic sensor. lsm303dlhc has linear a cceleration full-scales of 2 g / 4 g / 8 g / 16 g and a magnetic field full- scale of 1.3 / 1.9 / 2.5 / 4.0 / 4.7 / 5.6 / 8.1 gauss . all full-scales available are fully selectable by the user. lsm303dlhc includes an i 2 c serial bus interface that supports standard and fast mode 100 khz and 400khz. the system can be configured to generate interrupt signals by inertial wake- up/free-fall events as well as by the position of the device itself. thresholds and timing of interrupt generators are programmable by the end user on the fly. magnetic and accelerometer parts can be enabled or put into power-down mode separately. the lsm303dlhc is available in a plastic land grid array package (lga) and is guaranteed to operate over an extended temperature range from -40 c to +85 c. lga-14 (3x5x1mm) table 1. device summary part number temperature range [c] package packing lsm303dlhc -40 to +85 lga-14 tray LSM303DLHCTR -40 to +85 lga-14 tape and reel www.st.com
contents lsm303dlhc 2/42 doc id 018771 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.1 sensor i 2 c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.1 linear acceleration sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 digital interface power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 high current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.2 linear acceleration digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.3 magnetic field digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
lsm303dlhc contents doc id 018771 rev 1 3/42 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 linear acceleration register description . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.1 ctrl_reg1_a (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.2 ctrl_reg2_a (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1.3 ctrl_reg3_a (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1.4 ctrl_reg4_a (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.5 ctrl_reg5_a (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.6 ctrl_reg6_a (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1.7 reference/datacapture_a (26h) . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1.8 status_reg_a (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.9 out_x_l_a (28h), out_x_h_a (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.10 out_y_l_a (2ah), out_y_h_a (2bh) . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.11 out_z_l_a (2ch), out_z_h_a (2dh) . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.12 fifo_ctrl_reg_a (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.13 fifo_src_reg_a (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.14 int1_cfg_a (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.15 int1_src_a (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1.16 int1_ths_a (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1.17 int1_duration_a (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1.18 int2_cfg_a (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1.19 int2_src_a (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1.20 int2_ths_a (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.21 int2_duration_a (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.22 click_cfg_a (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.23 click_src_a (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.24 click_ths_a (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1.25 time_limit_a (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1.26 time_latency_a (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1.27 time window_a (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 magnetic field sensing register description . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.1 cra_reg_m (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.2 crb_reg_m (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.3 mr_reg_m (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.4 out_x_h_m (03), out_x_lh_m (04h) . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.5 out_z_h_m (05), out_z_l_m (06h) . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.6 out_y_h_m (07), out_y_l_m (08h) . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.7 sr_reg_m (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
contents lsm303dlhc 4/42 doc id 018771 rev 1 7.2.8 ir_reg_m (0ah/0bh/0ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.9 temp_out_h_m (31h), temp_out_l_m (32h) . . . . . . . . . . . . . . . . 39 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
lsm303dlhc list of tables doc id 018771 rev 1 5/42 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. accelerometer operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 12. transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 13. transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 19 table 14. sad+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 15. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 20 table 16. sad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 17. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 18. ctrl_reg1_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. ctrl_reg1_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 20. data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 21. ctrl_reg2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 22. ctrl_reg2_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 23. high pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 24. ctrl_reg3_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 25. ctrl_reg3_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 26. ctrl_reg4_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 27. ctrl_reg4_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 28. ctrl_reg5_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 29. ctrl_reg5_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 30. ctrl_reg6_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 31. ctrl_reg6_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 32. reference_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 33. reference_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 34. status_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 35. status_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 36. reference_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 37. reference_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 38. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 39. fifo_src_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 40. int1_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 41. int1_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 42. interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 43. int1_src_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 44. int1_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 45. int1_ths_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 46. int1_ths_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 47. int1_duration_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 48. int1_duration_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
list of tables lsm303dlhc 6/42 doc id 018771 rev 1 table 49. int2_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 50. int2_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 51. interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 52. int2_src_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 53. int2_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 54. int2_ths_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 55. int2_ths_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 56. int2_duration_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 57. int2_duration_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 58. click_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 59. click_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 60. click_src_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 61. click_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 62. click_ths_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 63. click_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 64. time_limit_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 65. time_limit_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 66. time_latency_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 67. time_latency_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 68. time_window_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 69. time_window_a description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 70. cra_reg_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 71. cra_reg_m description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 72. data rate configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 73. cra_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 74. cra_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 75. gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 76. mr_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 77. mr_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 79. sr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 80. sr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 81. ira_reg_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 82. irb_reg_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 83. irc_reg_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 84. temp_out_h_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 85. temp_out_l_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 86. temp_out resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 87. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
lsm303dlhc block diagram and pin description doc id 018771 rev 1 7/42 1 block diagram and pin description 1.1 block diagram figure 1. block diagram y+ z+ y- z- x+ x- mux s da s cl i ( a ) + - charge amplifier s en s ing block s en s ing interf a ce a/d control logic converter di i2c int1 int2 mux i (m) + - charge amplifier y+ z+ y- z- x+ x- interrupt gen. clock trimming circuit s reference off s et circuit s built-in circuit s s et/re s et temperature fifo s en s or am092 3 6v1
block diagram and pin description lsm303dlhc 8/42 doc id 018771 rev 1 1.2 pin description figure 2. pin connection table 2. pin description pin# name function 1 vdd_io power supply for i/o pins 2 scl signal interface i 2 c serial clock (scl) 3 sda signal interface i 2 c serial data (sda) 4 int2 inertial interrupt 2 5 int1 inertial interrupt 1 6 c1 reserved capacitor connection (c1) 7 gnd 0 v supply 8 reserved leave unconnected 9 drdy data ready 10 reserved connect to gnd 11 reserved connect to gnd 12 setp s/r capacitor connection (c2) 13 setc s/r capacitor connection (c2) 14 vdd power supply direction of detectable magnetic field s direction of detectable acceleration s 1 1 38 6 1 bottom view 1 3 8 6 top view x z y 1 1 3 8 6 top view x z y am092 3 7v1
lsm303dlhc module specifications doc id 018771 rev 1 9/42 2 module specifications 2.1 sensor characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (a) . a. the product is factory calibrated at 2.5 v. the ope rational power supply range is from 2.16 v to 3.6 v. table 3. sensor characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range (2) fs bit set to 00 2 g fs bit set to 01 4 fs bit set to 10 8 fs bit set to 11 16 m_fs magnetic measurement range gn bits set to 001 1.3 gauss gn bits set to 010 1.9 gn bits set to 011 2.5 gn bits set to 100 4.0 gn bits set to 101 4.7 gn bits set to 110 5.6 gn bits set to 111 8.1 la_so linear acceleration sensitivity fs bit set to 00 1 mg/lsb fs bit set to 01 2 fs bit set to 10 4 fs bit set to 11 12 m_gn magnetic gain setting gn bits set to 001 (x,y) 1100 lsb/ gauss gn bits set to 001 (z) 980 gn bits set to 010 (x,y) 855 gn bits set to 010 (z) 760 gn bits set to 011 (x,y) 670 gn bits set to 011 (z) 600 gn bits set to 100 (x,y) 450 gn bits set to 100 (z) 400 gn bits set to 101 (x,y) 400 gn bits set to 101 (z) 355 gn bits set to 110 (x,y) 330 gn bits set to 110 (z) 295 gn bits set to 111 (2) (x,y) 230 gn bits set to 111 (2) (z) 205
module specifications lsm303dlhc 10/42 doc id 018771 rev 1 2.2 temperature sensor characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (b) . la_tcso linear acceleration sensitivity change vs. temperature fs bit set to 00 0.01 %/c la_tyoff linear acceleration typical zero- g level offset accuracy (3),(4) fs bit set to 00 60 m g la_tcoff linear acceleration zero- g level change vs. temperature max. delta from 25 c 0.5 m g /c la_an acceleration noise density fs bit set to 00, normal mode( table 8. ), odr bit set to 1001 220 ug/ sqrt(hz) m_r magnetic resolution 2 mgauss m_cas magnetic cross-axis sensitivity cross field =.0.5 gauss h applied = 3 gauss 1 %fs/ gauss m_ef maximum exposed field no permitting effect on zero reading 10000 gauss m_df disturbing field sensitivity starts to degrade. use s/r pulse to restore sensitivity 20 gauss top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. verified by wafer level test and measurement of initial offset and sensitivity. 3. typical zero- g level offset value after msl3 preconditioning . 4. offset can be eliminated by enabling the built-in high pass filter . table 3. sensor characteristics (continued) symbol parameter test conditions min. typ. (1) max. unit b. the product is factory calibrated at 2.5 v. table 4. temperature sensor characteristics symbol parameter test condition min. typ. (1) max. unit tsdr temperature sensor output change vs. temperature - 8lsb/c (2) todr temperature refresh rate odr (3) hz top operating temperature range -40 +85 c 1. typical specificat ions are not guaranteed. 2. 12-bit resolution. 3. for odr configuration refer to table 72 .
lsm303dlhc module specifications doc id 018771 rev 1 11/42 2.3 electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted. table 5. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage - 2.16 3.6 v vdd_io module power supply for i/o 1.71 1.8 vdd+0.1 idd current consumption in normal mode (2) 110 a iddsl current consumption in sleep-mode (3) 1a top operating temperature range -40 +85 c 1. typical specifications are not guaranteed . 2. magnetic sensor setting odr = 7.5 hz, accelerometer sensor odr = 50 hz . 3. linear accelerometer in sleep-mode and magnetic sensor in power-down mode .
module specifications lsm303dlhc 12/42 doc id 018771 rev 1 2.4 communication interfaces characteristics external pull-up resistors are required to support i 2 c standard and fast speed modes. 2.4.1 sensor i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 3. i 2 c slave timing diagram (c) table 6. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b (2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 2. cb = total capacitance of one bus line, in pf. sda scl t f(sda) t su(sp) t w(scll) t su(sda) t r(sda) t su(sr) t h(st) t w(sclh) t h(sda) t r(scl) t f(scl) t w(sp:sr) start repeated start stop start am092 38 v1
lsm303dlhc module specifications doc id 018771 rev 1 13/42 2.5 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. c. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. table 7. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (scl, sda) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) 3,000 for 0.5 ms g 10,000 for 0.1 ms g a unp acceleration (any axis, unpowered) 3,000 for 0.5 ms g 10,000 for 0.1 ms g t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c this is a mechanical shock sensitive device, improper handling can cause permanent damage to the part. this is an esd sensitive device, improper handling can cause permanent damage to the part.
module specifications lsm303dlhc 14/42 doc id 018771 rev 1 2.6 terminology 2.6.1 linear accel eration sensitivity linear acceleration sensitivity describes the gain of the accelerometer sensor and can be determined by applying 1 g acceleration to it. as the sensor can measure dc accelerations, this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and also very little over time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 2.6.2 zero-g level zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady-state on a horizontal surface measures 0 g in the x axis and 0 g in the y axis whereas the z axis measures 1 g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is, to some extent, a result of stress to the mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero- g level change vs. temperature?. the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a population of sensors.
lsm303dlhc functionality doc id 018771 rev 1 15/42 3 functionality the lsm303dlhc is a system-in-package featuring a 3d digital linear acceleration and 3d digital magnetic field detection sensor. the system includes specific sensing element s and an ic interface capable of measuring both the linear acceleration and magnetic field applied on it and to provide a signal to the external world through an i 2 c serial interface with separated digital output. the sensing system is manufactured using specialized micromachining processes, while the ic interfaces are realized using a cmos technology that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics. the lsm303dlhc features two data-ready signals (rdy) which indicate when a new set of measured acceleration data and magnetic data are available, therefore simplifying data synchronization in the digital system that uses the device. the lsm303dlhc may also be configured to generate a free-fall interrupt signal according to a programmed acceleration event along the enabled axes. linear acceleration operating mode lsm303dlhc provides two different accelera tion operating modes, respectively reported as ?normal mode? and ?low-power mode?. while normal mode guarantees high resolution, low-power mode reduces further the current consumption. table 8 summarizes how to select the operating mode. 3.1 factory calibration the ic interface is factory calibrated for linear acceleration sensitivity (la_so), and linear acceleration zero-g level (la_tyoff). the trimming values are stored inside the device by a non-volatile memory. any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the normal operation. this allows the user to use the device without further calibration. table 8. accelerometer operating mode selection operating mode ctrl_reg1[3] (lpen bit) ctrl_reg4[3] (hr bit) bw [hz] turn-on time [ms] low-power mode 1 0 odr/2 1 normal mode 0 1 odr/9 7/odr
application hints lsm303dlhc 16/42 doc id 018771 rev 1 4 application hints figure 4. lsm303dlhc electrical connection 4.1 capacitors the c1 and c2 external capacitors should be low sr value ceramic type constructions (typ. suggested value 200 mohm). reservoir capacito r c1 is nominally 4.7 f in capacitance, with the set/reset capacitor c2 nominally 0.22 f in capacitance. the device core is supplied through the vdd line. power supply decoupling capacitors (c4=100 nf ceramic, c3=10 f al) should be placed as near as possible to the supply pin of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 4 ). the functionality of the device and the measured acceleration/magnetic field data is selectable and accessible through the i 2 c interface. the functions, the threshold, and the timing of the two interrupt pins (int 1 and int 2) can be completely programmed by the user through the i 2 c interface. 4.2 pull-up resistors pull-up resistors (suggested value 10 kohm) are placed on the two i 2 c bus lines. top view vdd_io int2 int1 6 1 s cl s da c1 c1=4.7 u f gnd 8 1 3 c2=0.22 u f vdd c4 = 100nf c 3 = 10 u f digit a l s ign a l from/to s ign a l controller. s ign a l s level s a re defined b y proper s election of vdd vdd i2c bus rp u rp u 10kohm 10kohm 1 1 3 8 6 top view x z y 1 1 3 8 6 top view x z y drdy am092 3 9v1
lsm303dlhc application hints doc id 018771 rev 1 17/42 4.3 digital interface power supply this digital interface, dedicated to the linear acceleration and to the magnetic field signal, is capable of operating with a standard power supply (vdd) or using a dedicated power supply (vdd_io). 4.4 soldering information the lga package is compliant with the ecopack ? , rohs, and ?green? standard. it is qualified for soldering heat resist ance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com/mems . 4.5 high current wiring effects high current in the wiring and printed circuit trace can be culprits in causing errors in magnetic field measurements for compassing. conductor generated magnetic fields add to th e earth?s magnetic field, causing errors in compass heading computation. keep currents higher than 10 ma a few m illimeters further away from the sensor ic.
digital interfaces lsm303dlhc 18/42 doc id 018771 rev 1 5 digital interfaces the registers embedded inside the lsm303dlhc are accessible through two separate i 2 c serial interfaces, one for the accelerometer core and one for the magnetometer core. 5.1 i 2 c serial interface the lsm303dlhc i 2 c is a bus slave. the i 2 c is employed to write the data into the registers whon also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus, the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. table 9. serial interface pin description pin name pin description scl i 2 c serial clock (scl) sda i 2 c serial data (sda) table 10. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals, and terminates a transfer slave the device addressed by the master
lsm303dlhc digital interfaces doc id 018771 rev 1 19/42 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and bit 8 tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in th e system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the lsm303dlhc behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-a ddress (sub) is transmitted; the 7 lsbs represent the actual register address while the msb enables address auto- increment. if the msb of the sub field is ?1?, the sub (register address) is automatically increased to allow mult iple data read/write. data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. table 11. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 12. transfer when master is writing multiple bytes to slave: master st sad + w sub data data sp slave sak sak sak sak table 13. transfer when master is receiving (reading) one byte of data from slave: master st sad + w sub sr sad + r nmak sp slave sak sak sak data
digital interfaces lsm303dlhc 20/42 doc id 018771 rev 1 5.1.2 linear accelera tion digital interface for linear acceleration the default (factory) 7-bit slave address is 0011001b. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master transmits to the slave with the direction unchanged. table 14 explains how the ead/write bit pattern is composed, listing all the possible configurations. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of the first register to be read. in the presented communication format, mak is master acknowledge and nmak is no master acknowledge. table 14. sad+read/write patterns command sad[7:1] r/w sad+r/w read 0011001 1 00110011 (33h) write 0011001 0 00110010 (32h) table 15. transfer when master is receiving (reading) multiple bytes of data from slave master st sad +w sub sr sad +r mak mak nmak sp slave sak sak sak data data data
lsm303dlhc digital interfaces doc id 018771 rev 1 21/42 5.1.3 magnetic fiel d digital interface for magnetic sensors the default (factory) 7-bit slave address is 0011110xb. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master transmits to the slave with the direction unchanged. table 16 explains how the sad is composed. magnetic signal interface reading/writing the interface uses an address pointer to indicate which register location is to be read from or written to. these pointer locations are sent from the master to this slave device and succeed the 7-bit address plus 1 bit read/write identifier. to minimize the communication between the master and magnetic digital interface of lsm303dlhc, the address pointer updates automatically without master intervention. this automatic address pointer update has two additional features. first, when address 12 or higher is accessed, the pointer updates to address 00, and secondly, when address 08 is reached, the pointer rolls back to address 03. logically, the address pointer operation functions as shown below. if (address pointer = 08) then the address pointer = 03 or else, if (address pointer >= 12) then the address pointer = 0 or else, (address pointer) = (address pointer) + 1 the address pointer value itself cannot be read via the i 2 c bus. any attempt to read an invalid address location returns 0, and any write to an invalid address location, or an undefined bit within a valid address location, is ignored by this device. table 16. sad command sad[6:0] r/w sad+r/w read 0011110 1 00111101 (3dh) write 0011110 0 00111100 (3ch)
register mapping lsm303dlhc 22/42 doc id 018771 rev 1 6 register mapping table 17 provides a listing of the 8-bit registers embedded in the device and the related addresses: table 17. register address map name slave address type register address default comment hex binary reserved (do not modify) table 14 00 - 1f -- -- reserved ctrl_reg1_a table 14 rw 20 010 0000 00000111 ctrl_reg2_a table 14 rw 21 010 0001 00000000 ctrl_reg3_a table 14 rw 22 010 0010 00000000 ctrl_reg4_a table 14 rw 23 010 0011 00000000 ctrl_reg5_a table 14 rw 24 010 0100 00000000 ctrl_reg6 _a table 14 rw 25 010 0101 00000000 reference_a table 14 rw 26 010 0110 00000000 status_reg_a table 14 r 27 010 0111 00000000 out_x_l_a table 14 r 28 010 1000 output out_x_h_a table 14 r 29 010 1001 output out_y_l_a table 14 r 2a 010 1010 output out_y_h_a table 14 r 2b 010 1011 output out_z_l_a table 14 r 2c 010 1100 output out_z_h_a table 14 r 2d 010 1101 output fifo_ctrl_reg_a table 14 rw 2e 010 1110 00000000 fifo_src_reg_a table 14 r 2f 010 1111 int1_cfg_a table 14 rw 30 011 0000 00000000 int1_source_a table 14 r 31 011 0001 00000000 int1_ths_a table 14 rw 32 011 0010 00000000 int1_duration_a table 14 rw 33 011 0011 00000000 int2_cfg_a table 14 rw 34 011 0100 00000000 int2_source_a table 14 r 35 011 0101 00000000 int2_ths_a table 14 rw 36 011 0110 00000000 int2_duration_a table 14 rw 37 011 0111 00000000 click_cfg_a table 14 rw 38 011 1000 00000000 click_src_a table 14 rw 39 011 1001 00000000 click_ths_a table 14 rw 3a 011 1010 00000000 time_limit_a table 14 rw 3b 011 1011 00000000
lsm303dlhc register mapping doc id 018771 rev 1 23/42 registers marked as ?reserved? must not be changed. the writing to these registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibrated values. their content is automatically restored when the device is powered up. time_latency_a table 14 rw 3c 011 1100 00000000 time_window_a table 14 rw 3d 011 1101 00000000 reserved (do not modify) table 14 3e-3f -- -- reserved cra_reg_m table 16 rw 00 00000000 0001000 crb_reg_m table 16 rw 01 00000001 0010000 mr_reg_m table 16 rw 02 00000010 00000011 out_x_h_m table 16 r 03 00000011 output out_x_l_m table 16 r 04 00000100 output out_z_h_m table 16 r 05 00000101 output out_z_l_m table 16 r 06 00000110 output out_y_h_m table 16 r 07 00000111 output out_y_l_m table 16 r 08 00001000 output sr_reg_mg table 16 r 09 00001001 00000000 ira_reg_m table 16 r 0a 00001010 01001000 irb_reg_m table 16 r 0b 00001011 00110100 irc_reg_m table 16 r 0c 00001100 00110011 reserved (do not modify) table 16 0d-30 -- -- reserved temp_out_h_m table 16 31 00000000 output temp_out_l_m table 16 32 00000000 output reserved (do not modify) table 16 33-3a -- -- reserved table 17. register address map (continued) name slave address type register address default comment hex binary
register description lsm303dlhc 24/42 doc id 018771 rev 1 7 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the register address, made up of 7 bits, is used to identify them and to write the data through the serial interface. 7.1 linear acceleration register description 7.1.1 ctrl_reg1_a (20h) odr<3:0> is used to set the power mode and odr selection. in table 20 all frequencies resulting in a combinatio n of odr<3:0> are listed. table 18. ctrl_reg1_a register odr3 odr2 odr1 odr0 lpen zen yen xen table 19. ctrl_reg1_a description odr3-0 data rate selection. default value: 0 (0000: power-down, others: refer to table 20. ) lpen low-power mode enable. default value: 0 (0: normal mode, 1: low-power mode) zen z axis enable. default value: 1 (0: z axis disabled, 1: z axis enabled) ye n y axis enable. default value: 1 (0: y axis disabled, 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled, 1: x axis enabled) table 20. data rate configuration odr3 odr2 odr1 odr0 power mode selection 0000power-down mode 0 0 0 1 normal / low-power mode (1 hz) 0 0 1 0 normal / low-power mode (10 hz) 0 0 1 1 normal / low-power mode (25 hz) 0 1 0 0 normal / low-power mode (50 hz) 0 1 0 1 normal / low-power mode (100 hz) 0 1 1 0 normal / low-power mode (200 hz) 0 1 1 1 normal / low-power mode (400 hz)
lsm303dlhc register description doc id 018771 rev 1 25/42 7.1.2 ctrl_reg2_a (21h) 7.1.3 ctrl_reg3_a (22h) 1000low-power mode (1.620 khz) 1 0 0 1 normal (1.344 khz) / low-power mode (5.376 khz) table 20. data rate configuration (continued) odr3 odr2 odr1 odr0 power mode selection table 21. ctrl_reg2_a register hpm1 hpm0 hpcf2 hpcf1 fds hpclick hpis2 hpis1 table 22. ctrl_reg2_a description hpm1 -hpm0 high pass filter mode selection. default value: 00 (refer to table 23 ) hpcf2 - hpcf1 high pass filter cut-off frequency selection fds filtered data selection. default value: 0 (0: internal filter bypassed, 1: data from in ternal filter sent to output register and fifo) hpclick high pass filter enabled for click function. (0: filter bypassed, 1: filter enabled) hpis2 high pass filter enabled for aoi function on interrupt 2, (0: filter bypassed, 1: filter enabled) hpis1 high pass filter enabled for aoi function on interrupt 1, (0: filter bypassed, 1: filter enabled) table 23. high pass filter mode configuration hpm1 hpm0 high pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode 1 1 autoreset on interrupt event table 24. ctrl_reg3_a register i1_click i1_aoi1 i1_aoi2 i1_drdy1 i1_drdy2 i1_wtm i1_overrun --
register description lsm303dlhc 26/42 doc id 018771 rev 1 7.1.4 ctrl_reg4_a (23h) 7.1.5 ctrl_reg5_a (24h) table 25. ctrl_reg3_a description i1_click click interrupt on int1. default value 0. (0: disable, 1: enable) i1_aoi1 aoi1 interrupt on int1. default value 0. (0: disable, 1: enable) i1_aoi2 aoi2 interrupt on int1. default value 0. (0: disable, 1: enable) i1_drdy1 drdy1 interrupt on int1. default value 0. (0: disable, 1: enable) i1_drdy2 drdy2 interrupt on int1. default value 0. (0: disable, 1: enable) i1_wtm fifo watermark interrupt on int1. default value 0. (0: disable, 1: enable) i1_overrun fifo overrun interrupt on int1. default value 0. (0: disable, 1: enable) table 26. ctrl_reg4_a register bdu ble fs1 fs0 hr 0 (1) 1. this bit must be set to ?0? for correct working of the device. 0 (1) sim table 27. ctrl_reg4_a description bdu block data update. default value: 0 (0: continuos update, 1: output r egisters not updated until msb and lsb reading ble big/little endian data selection. default value 0. (0: data lsb @ lower address, 1: data msb @ lower address) fs1-fs0 full-scale selection. default value: 00 (00: +/- 2g, 01: +/- 4g, 10: +/- 8g, 11: +/- 16g) hr high resolution output mode: default value: 0 (0: high resolution disable, 1: high resolution enable) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface, 1: 3-wire interface). table 28. ctrl_reg5_a register boot fifo_en -- -- lir_int1 d4d_int1 lir_int2 d4d_int2
lsm303dlhc register description doc id 018771 rev 1 27/42 7.1.6 ctrl_reg6_a (25h) 7.1.7 reference/dat acapture_a (26h) table 29. ctrl_reg5_a description boot reboot memory content. default value: 0 (0: normal mode, 1: reboot memory content) fifo_en fifo enable. default value: 0 (0: fifo disable, 1: fifo enable) lir_int1 latch interrupt request on int 1_src register, with int1_src register cleared by reading int1_src itself. default value: 0. (0: interrupt request not latched, 1: interrupt request latched) d4d_int1 4d enable: 4d detection is enabled on int1 when 6d bit on int1_cfg is set to 1. lir_int2 latch interrupt request on int 2_src register, with int2_src register cleared by reading int2_src itself. default value: 0. (0: interrupt request not latched, 1: interrupt request latched) d4d_int2 4d enable: 4d detection is enabled on int2 when 6d bit on int2_cfg is set to 1. table 30. ctrl_reg6_a register i2_clicken i2_int1 i2_int2 boot_i1 p2_act - - h_lactive -- table 31. ctrl_reg6_a description i2_clicken click interrupt on pad2. default value 0. (0: disable, 1: enable) i2_int1 interrupt 1 on pad2. default value 0. (0: disable, 1: enable) i2_int2 interrupt 2 on pad2. default value 0. (0: disable, 1: enable) boot_i1 reboot memory content on pad2. default value: 0 (0: disable, 1: enable) p2_act active function status on pad2. default value 0. (0: disable, 1: enable) h_lactive interrupt active high, low. default value 0. (0: active high, 1: active low) table 32. reference_a register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0
register description lsm303dlhc 28/42 doc id 018771 rev 1 7.1.8 status_reg_a (27h) 7.1.9 out_x_l_a (28h ), out_x_h_a (29h) x-axis acceleration data. the value is expressed in 2?s complement. 7.1.10 out_y_l_a (2ah ), out_y_h_a (2bh) y-axis acceleration data. the value is expressed in 2?s complement. 7.1.11 out_z_l_a (2ch), out_z_h_a (2dh) z-axis acceleration data. the value is expressed in 2?s complement. table 33. reference_a register description ref 7-ref0 reference value for interrupt generation. default value: 0 table 34. status_a register zyxor zor yor xor zyxda zda yda xda table 35. status_a register description zyxor x, y, and z axis data overrun. default value: 0 (0: no overrun has occurred, 1: a new set of data has overwritten the previous ones) zor z axis data overrun. default value: 0 (0: no overrun has occurred, 1: a new data for the z-axis has overwritten the previous one) yor y axis data overrun. default value: 0 (0: no overrun has occurred, 1: a new data for the y-axis ha s overwritten the previous one) xor x axis data overrun. default value: 0 (0: no overrun has occurred, 1: a new data for the x-axis ha s overwritten the previous one) zyxda x, y, and z axis new data available. default value: 0 (0: a new set of data is not yet available, 1: a new set of data is available) zda z axis new data available. default value: 0 (0: a new data for the z-axis is not yet available, 1: a new data for the z-axis is available) yda y axis new data available. default value: 0 (0: a new data for the y-axis is not yet available, 1: a new data for the y-axis is available) xda x axis new data available. default value: 0 (0: a new data for the x-axis is not yet available, 1: a new data for the x-axis is available)
lsm303dlhc register description doc id 018771 rev 1 29/42 7.1.12 fifo_ctrl_reg_a (2eh) 7.1.13 fifo_src_reg_a (2fh) 7.1.14 int1_cfg_a (30h) table 36. reference_a register fm1 fm0 tr fth4 fth3 fth2 fth1 fth0 table 37. reference_a register description fm1-fm0 fifo mode selection. default value: 00 (see table 38 ) tr trigger selection. default value: 0 0: trigger event linked to trigger signal on int1 1: trigger event linked to trigger signal on int2 fth4:0 default value: 0 table 38. fifo mode configuration fm1 fm0 fifo mode configuration 0 0 bypass mode 0 1 fifo mode 1 0 stream mode 1 1 trigger mode table 39. fifo_src_a register wtm ovrn_fifo empty fss4 fss3 fss2 fss1 fss0 table 40. int1_cfg_a register aoi 6d zhie/ zupe zlie/ zdowne yhie/ yupe ylie/ ydowne xhie/ xupe xlie/ xdowne table 41. int1_cfg_a description aoi and/or combination of interrupt events. default value: 0 (refer to table 42 ) 6d 6-direction detection function enab led. default value: 0 (refer to table 42 ) zhie/ zupe enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request, 1: enable interrupt request) zlie/ zdowne enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request, 1: enable interrupt request)
register description lsm303dlhc 30/42 doc id 018771 rev 1 content of this register is loaded at boot. wr ite operation at this address is possible only after system boot. difference between aoi-6d = ?01? and aoi-6d = ?11?. aoi-6d = ?01? is movement recognition. an interrupt is generated when orientation moves from unknown zone to known zone. the interrupt signal stays for a duration odr. aoi-6d = ?11? is direction recognition. an inte rrupt is generated when orientation is inside a known zone. the interrupt signal stays until orientation is inside the zone. 7.1.15 int1_src_a (31h) yhie/ yupe enable interrupt generation on y high event or on direction recognition. default value: 0 (0: disable interrupt request, 1: enable interrupt request.) ylie/ ydowne enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request, 1: enable interrupt request.) xhie/ xupe enable interrupt generation on x high event or on direction recognition. default value: 0 (0: disable interrupt request, 1: enable interrupt request.) xlie/xdowne enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request, 1: enable interrupt request.) table 42. interrupt mode aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition table 41. int1_cfg_a description (continued) table 43. int1_src_a register 0 (1) 1. this bit must be set to ?0? for correct working of the device. ia zh zl yh yl xh xl table 44. int1_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated, 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt, 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred)
lsm303dlhc register description doc id 018771 rev 1 31/42 interrupt 1 source register. read only register. reading at this address clears the int1_src ia bit (and the interrupt signal on the int 1 pin) and allows the refreshing of data in the int1_src register if the latched option was chosen. 7.1.16 int1_ths_a (32h) 7.1.17 int1_duration_a (33h) d6 - d0 bits set the minimum duration of the interrupt 1 event to be recognized. duration steps and maximum values depend on the odr chosen. 7.1.18 int2_cfg_a (34h) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 44. int1_src_a description (continued) table 45. int1_ths_a register 0 (1) 1. this bit must be set to ?0? for correct working of the device. ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 46. int1_ths_a description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 47. int1_duration_a register 0 (1) 1. this bit must be set to ?0? for correct working of the device. d6 d5 d4 d3 d2 d1 d0 table 48. int1_duration_a description d6 - d0 duration value. default value: 000 0000 table 49. int2_cfg_a register aoi 6d zhie zlie yhie ylie xhie xlie
register description lsm303dlhc 32/42 doc id 018771 rev 1 difference between aoi-6d = ?01? and aoi-6d = ?11?. aoi-6d = ?01? is movement recognition. an interrupt is generated when orientation moves from unknown zone to known zone. the interrupt signal stays for a duration odr. aoi-6d = ?11? is direction recognition. an inte rrupt is generated when orientation is inside a known zone. the interrupt signal stays until orientation is inside the zone. 7.1.19 int2_src_a (35h) table 50. int2_cfg_a description aoi and/or combination of interrupt events. default value: 0 (see table 51 ) 6d 6-direction detection function enabled. default value: 0 (refer to table 51 ) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value lower than preset threshold) table 51. interrupt mode aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition table 52. int2_src_a register 0 (1) 1. this bit must be set to ?0? for correct working of the device. ia zh zl yh yl xh xl
lsm303dlhc register description doc id 018771 rev 1 33/42 interrupt 2 source register. read only register. reading at this address clears int2_src ia bit (and the interrupt signal on the int 2 pin) and allows the refreshing of data in the int2_src register if the latched option was chosen. 7.1.20 int2_ths_a (36h) 7.1.21 int2_duration_a (37h) table 53. int2_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated, 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt, 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 54. int2_ths_a register 0 (1) 1. this bit must be set to ?0? for correct working of the device ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 55. int2_ths_a description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 56. int2_duration_a register 0 (1) 1. this bit must be set to ?0? for correct working of the device d6 d5 d4 d3 d2 d1 d0 table 57. int2_duration_a description d6-d0 duration value. default value: 000 0000
register description lsm303dlhc 34/42 doc id 018771 rev 1 d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration time steps and maximum values depend on the odr chosen. 7.1.22 click_cfg_a (38h) 7.1.23 click_ src_a (39h) table 58. click_cfg_a register -- -- zd zs yd ys xd xs table 59. click_cfg_a description zd enable interrupt double click on z axis. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) zs enable interrupt single click on z axis. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) yd enable interrupt double click on y axis. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) ys enable interrupt single click on y axis. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) xd enable interrupt double click on x axis. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) xs enable interrupt single click on x axis. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) table 60. click_src_a register -- ia dclick sclick sign z y x table 61. click_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated, 1: one or more interrupts have been generated) dclick double click-click enable. default value: 0 (0:double click-click detection dis- able, 1: double click-click detection enable) sclick single click-click enable. default value: 0 (0:single click-click detection dis- able, 1: single click-click detection enable) sign click-click sign. 0: positive detection, 1: negative detection
lsm303dlhc register description doc id 018771 rev 1 35/42 7.1.24 click_ths_a (3ah) 1 lsb = full-scale / 128. ths6 through ths0 define the threshold which is used by the system to start the click detection procedure. the threshold value is expressed over 7 bits as an unsigned number. 7.1.25 time_limit_a (3bh) 1 lsb = 1/odr. tli7 through tli0 define the maximum time interval that can elapse between the start of the click detection procedure (the acceleration on the selected channel exceeds the programmed threshold) and when the acceleration goes back below the threshold. 7.1.26 time_l atency_a (3ch) z z click-click detection. default value: 0 (0: no interrupt, 1: z high event has occurred) y y click-click detecti on. default value: 0 (0: no interrupt, 1: y high event has occurred) x x click-click detecti on. default value: 0 (0: no interrupt, 1: x high event has occurred) table 61. click_src_a description (continued) table 62. click_ths_a register -- ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 63. click_src_a description ths6-ths0 click-click threshold. default value: 000 0000 table 64. time_limit_a register -- tli6 tli5 tli4 tli3 tli2 tli1 tli0 table 65. time_limit_a description tli7-tli0 click-click time li mit. default value: 000 0000 table 66. time_latency_a register tla7 tla6 tla5 tla4 tla3 tla2 tla1 tla0 table 67. time_latency_a description tla7-tla0 click-click time latency. default value: 000 0000
register description lsm303dlhc 36/42 doc id 018771 rev 1 1 lsb = 1/odr. tla7 through tla0 define the time interval that starts after the first click detection where the click detection procedure is disabled, in cases where the device is configured for double click detection. 7.1.27 time window_a (3dh) 1 lsb = 1/odr. tw7 through tw0 define the maximum interval of time that can elapse after the end of the latency interval in which the click detection procedure can start, in cases where the device is configured for double click detection. 7.2 magnetic field sensing register description 7.2.1 cra_reg_m (00h) table 68. time_window_a register tw7 tw6 tw5 tw4 tw3 tw2 tw1 tw0 table 69. time_window_a description tw7-tw0 click-click time window table 70. cra_reg_m register temp_en 0 (1) 1. this bit must be set to ?0? for correct working of the device 0 (1) do2 do1 do0 0 (1) 0 (1) table 71. cra_reg_m description temp _en temperature sensor enable. 0: temperature sensor disabled (default), 1: temperature sensor enabled do2 to do0 data output rate bits. these bits set the rate at which data is written to all three data output registers (refer to table 72 ). default value: 100 table 72. data rate configurations do2 do1 do0 minimum data output rate (hz) 00 0 0.75 00 1 1.5 01 0 3.0 01 1 7.5 1 0 0 15 10 1 30
lsm303dlhc register description doc id 018771 rev 1 37/42 7.2.2 crb_reg_m (01h) 7.2.3 mr_reg_m (02h) 11 0 75 11 1 220 table 72. data rate configurations (continued) do2 do1 do0 minimum data output rate (hz) table 73. cra_reg register gn2 gn1 gn0 0 (1) 1. this bit must be set to ?0? for correct working of the device. 0 (1) 0 (1) 0 (1) 0 (1) table 74. cra_reg description gn1-0 gain configuration bits. the gain configurat ion is common for all channels (refer to table 75 ) table 75. gain setting gn2 gn1 gn0 sensor input field range [gauss] gain x, y, and z [lsb/gauss] gain z [lsb/gauss] output range 001 1.3 1100 980 0xf800?0x07ff (-2048?2047) 0 1 0 1.9 855 760 0 1 1 2.5 670 600 1 0 0 4.0 450 400 1 0 1 4.7 400 355 1 1 0 5.6 330 295 1 1 1 8.1 230 205 table 76. mr_reg 0 (1) 1. this bit must be set to ?0? for correct working of the device. 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) md1 md0 table 77. mr_reg description md1-0 mode select bits. these bits select the operation mode of this device (refer to table 78 )
register description lsm303dlhc 38/42 doc id 018771 rev 1 7.2.4 out_x_h_m (03) , out_x_lh_m (04h) x-axis magnetic field data. the value is expressed as 2?s complement. 7.2.5 out_z_h_m (05), out_z_l_m (06h) z-axis magnetic field data. the val ue is expressed as 2?s complement. 7.2.6 out_y_h_m (0 7), out_y_l_m (08h) y-axis magnetic field data. the val ue is expressed as 2?s complement. 7.2.7 sr_reg_m (09h) 7.2.8 ir_reg_m (0ah/0bh/0ch) table 78. magnetic sensor operating mode md1 md0 mode 0 0 continuous-conversion mode 0 1 single-conversion mode 1 0 sleep-mode. device is placed in sleep-mode 1 1 sleep-mode. device is placed in sleep-mode table 79. sr register -- -- -- -- -- -- lock drdy table 80. sr register description lock data output register lock. once a new set of measurements is available, this bit is set when the first magnetic file data register has been read. drdy data ready bit. this bit is when a new set of measurements are available. table 81. ira_reg_m 01001000 table 82. irb_reg_m 00110100 table 83. irc_reg_m 00110011
lsm303dlhc register description doc id 018771 rev 1 39/42 7.2.9 temp_out_h_m (3 1h), temp_out_l_m (32h) table 84. temp_out_h_m register temp11 temp10 temp9 temp8 temp7 temp6 temp5 temp4 table 85. temp_out_l_m register temp3 temp2 temp1 temp0 -- -- -- -- table 86. temp_out resolution temp11-0 temperature data (8lsb/ deg - 12-bit resolution). the value is expressed as 2?s complement .
package information lsm303dlhc 40/42 doc id 018771 rev 1 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions, and product status are available at: www.st.com. ecopack is an st trademark. figure 5. lga-14: mechanical data and package dimensions dimens ions ref. mm min. typ. max. a1 1 a2 0.7 8 5 a 3 0.16 0.2 0.24 d1 2. 8 5 33 .15 e1 4. 8 555.15 n1 0. 8 l1 4 t1 0. 8 t2 0.5 m 0.1 k 0.05 lga 3 x5x1 14l land grid array packa g e outline and 8265271_a mechanical data
lsm303dlhc revision history doc id 018771 rev 1 41/42 9 revision history table 87. document revision history date revision changes 21-apr-2011 1 initial release.
lsm303dlhc 42/42 doc id 018771 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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